A 10-Bit 100MSPS 0.35 μm Si CMOS pipeline ADC

Qi Yu, Xiang Zhan Wang, Ning Ning, Lin Tang, Hong Bin Li, Mo Hua Yang

Research output: Contribution to conferencePaperpeer-review

3 Scopus citations

Abstract

Based on the principle of Pipeline ADC, a 4-4-4-bit three-stage 10-bit pipeline analog-to-digital converter (ADC) is presented. Combining with bootstrap circuit and bottom-plate sampling technology, a high linearity on-chip sample-and-hold (S/H) is realized. The preamplifier-latch comparator of the 4-bit flash sub-ADCs is implemented to reduce the comparator latch offset by using zero-crossing technique. In order to reduce common-mode interference, clock feed-through and even order distortion, the full-differential operational trails-conductance amplifiers (OTA) are designed for the residue and S/H circuits. The simulation results show that this ADC achieves over 70dB SFDR with 50MHz Nyquist input frequency at 100MSample/s (MSPS). Fabricated by standard 0.35um 2P3M mixed signal silicon CMOS process, the circuit occupies an area of 12.7mm2.

Original languageEnglish
Pages1523-1525
Number of pages3
StatePublished - 2004
Event2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 - Beijing, China
Duration: 18 Oct 200421 Oct 2004

Conference

Conference2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004
Country/TerritoryChina
CityBeijing
Period18/10/0421/10/04

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