A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS

Yuan Du; Wei Han Cho; Yilei Li; Chien Heng Wong; Jieqiong Du; Po Tsang Huang; Yanghyo Kim; Zuow Zun Chen; Sheau Jiung Lee; Mau Chung Frank Chang

doi:10.1109/VLSIC.2016.7573523

A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS

Yuan Du
, Wei Han Cho
, Yilei Li
, Chien Heng Wong
, Jieqiong Du
, Po Tsang Huang
, Yanghyo Kim
, Zuow Zun Chen
, Sheau Jiung Lee
, Mau Chung Frank Chang

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm² in 28nm CMOS. It achieves a maximum data rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 μW/Gb/s/dB considering channel condition.

Original language	English
Title of host publication	2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
ISBN (Electronic)	9781509006342
DOIs	https://doi.org/10.1109/VLSIC.2016.7573523
State	Published - 21 Sep 2016
Event	30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 - Honolulu, United States Duration: 14 Jun 2016 → 17 Jun 2016

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2016-September

Conference

Conference	30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016
Country/Territory	United States
City	Honolulu
Period	14/06/16 → 17/06/16

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/VLSIC.2016.7573523

Cite this

Du, Y., Cho, W. H., Li, Y., Wong, C. H., Du, J., Huang, P. T., Kim, Y., Chen, Z. Z., Lee, S. J., & Chang, M. C. F. (2016). A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS. In 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 Article 7573523 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2016-September). https://doi.org/10.1109/VLSIC.2016.7573523

@inproceedings{88646ab356db47838fd5079d93264545,

title = "A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS",

abstract = "A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm2 in 28nm CMOS. It achieves a maximum data rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 μW/Gb/s/dB considering channel condition.",

author = "Yuan Du and Cho, \{Wei Han\} and Yilei Li and Wong, \{Chien Heng\} and Jieqiong Du and Huang, \{Po Tsang\} and Yanghyo Kim and Chen, \{Zuow Zun\} and Lee, \{Sheau Jiung\} and Chang, \{Mau Chung Frank\}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016 ; Conference date: 14-06-2016 Through 17-06-2016",

year = "2016",

month = sep,

day = "21",

doi = "10.1109/VLSIC.2016.7573523",

language = "English",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

booktitle = "2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016",

}

Du, Y, Cho, WH, Li, Y, Wong, CH, Du, J, Huang, PT, Kim, Y, Chen, ZZ, Lee, SJ & Chang, MCF 2016, A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS. in 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016., 7573523, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2016-September, 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016, Honolulu, United States, 14/06/16. https://doi.org/10.1109/VLSIC.2016.7573523

A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS. / Du, Yuan; Cho, Wei Han; Li, Yilei et al.
2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016. 2016. 7573523 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2016-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS

AU - Du, Yuan

AU - Cho, Wei Han

AU - Li, Yilei

AU - Wong, Chien Heng

AU - Du, Jieqiong

AU - Huang, Po Tsang

AU - Kim, Yanghyo

AU - Chen, Zuow Zun

AU - Lee, Sheau Jiung

AU - Chang, Mau Chung Frank

PY - 2016/9/21

Y1 - 2016/9/21

N2 - A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm2 in 28nm CMOS. It achieves a maximum data rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 μW/Gb/s/dB considering channel condition.

AB - A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm2 in 28nm CMOS. It achieves a maximum data rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 μW/Gb/s/dB considering channel condition.

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DO - 10.1109/VLSIC.2016.7573523

M3 - Conference contribution

AN - SCOPUS:84990922556

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

BT - 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016

T2 - 30th IEEE Symposium on VLSI Circuits, VLSI Circuits 2016

Y2 - 14 June 2016 through 17 June 2016

ER -

Du Y, Cho WH, Li Y, Wong CH, Du J, Huang PT et al. A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS. In 2016 IEEE Symposium on VLSI Circuits, VLSI Circuits 2016. 2016. 7573523. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2016.7573523

A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS

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