A 32-Gb/s C2C-DAC-Based PAM-4 Wireline Transmitter with Two-Tap Feed-Forward Equalization and Level-Mismatch Correction in 28-nm CMOS

Boyu Hu; Yanghyo Kim; Rulin Huang; Yuan Du; Mau Chung Frank Chang

doi:10.1109/LMWC.2018.2870931

A 32-Gb/s C2C-DAC-Based PAM-4 Wireline Transmitter with Two-Tap Feed-Forward Equalization and Level-Mismatch Correction in 28-nm CMOS

Boyu Hu
, Yanghyo Kim
, Rulin Huang
, Yuan Du
, Mau Chung Frank Chang

Department of Electrical and Computer Engineering

University of California at Los Angeles

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

This letter presents a C2C-DAC-based PAM-4 wireline transmitter that utilizes capacitor-weighting within a predriver stage for multitap multilevel signal summation in charge domain at the transmitter front end. Such a unique approach isolates the signal summing node from the output to alleviate bandwidth limitation and also inherently provides passive voltage-scaling and level-shifting at the predriver output without sacrificing its speed. A level-mismatch-correction scheme is adopted to effectively enhance PAM-4 signaling quality. Implemented in a 28-nm CMOS, the designed transmitter prototype achieves a peak data rate of 32 Gb/s and an energy efficiency of 2.1 mW/Gb/s.

Original language	English
Article number	8476164
Pages (from-to)	1056-1058
Number of pages	3
Journal	IEEE Microwave and Wireless Components Letters
Volume	28
Issue number	11
DOIs	https://doi.org/10.1109/LMWC.2018.2870931
State	Published - Nov 2018

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

C2C-DAC
PAM-4
feed-forward equalization
level-mismatch correction
transmitter

Access to Document

10.1109/LMWC.2018.2870931

Cite this

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title = "A 32-Gb/s C2C-DAC-Based PAM-4 Wireline Transmitter with Two-Tap Feed-Forward Equalization and Level-Mismatch Correction in 28-nm CMOS",

abstract = "This letter presents a C2C-DAC-based PAM-4 wireline transmitter that utilizes capacitor-weighting within a predriver stage for multitap multilevel signal summation in charge domain at the transmitter front end. Such a unique approach isolates the signal summing node from the output to alleviate bandwidth limitation and also inherently provides passive voltage-scaling and level-shifting at the predriver output without sacrificing its speed. A level-mismatch-correction scheme is adopted to effectively enhance PAM-4 signaling quality. Implemented in a 28-nm CMOS, the designed transmitter prototype achieves a peak data rate of 32 Gb/s and an energy efficiency of 2.1 mW/Gb/s.",

keywords = "C2C-DAC, PAM-4, feed-forward equalization, level-mismatch correction, transmitter",

author = "Boyu Hu and Yanghyo Kim and Rulin Huang and Yuan Du and Chang, \{Mau Chung Frank\}",

note = "Publisher Copyright: {\textcopyright} 2001-2012 IEEE.",

year = "2018",

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doi = "10.1109/LMWC.2018.2870931",

language = "English",

volume = "28",

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AU - Hu, Boyu

AU - Kim, Yanghyo

AU - Huang, Rulin

AU - Du, Yuan

AU - Chang, Mau Chung Frank

PY - 2018/11

Y1 - 2018/11

N2 - This letter presents a C2C-DAC-based PAM-4 wireline transmitter that utilizes capacitor-weighting within a predriver stage for multitap multilevel signal summation in charge domain at the transmitter front end. Such a unique approach isolates the signal summing node from the output to alleviate bandwidth limitation and also inherently provides passive voltage-scaling and level-shifting at the predriver output without sacrificing its speed. A level-mismatch-correction scheme is adopted to effectively enhance PAM-4 signaling quality. Implemented in a 28-nm CMOS, the designed transmitter prototype achieves a peak data rate of 32 Gb/s and an energy efficiency of 2.1 mW/Gb/s.

AB - This letter presents a C2C-DAC-based PAM-4 wireline transmitter that utilizes capacitor-weighting within a predriver stage for multitap multilevel signal summation in charge domain at the transmitter front end. Such a unique approach isolates the signal summing node from the output to alleviate bandwidth limitation and also inherently provides passive voltage-scaling and level-shifting at the predriver output without sacrificing its speed. A level-mismatch-correction scheme is adopted to effectively enhance PAM-4 signaling quality. Implemented in a 28-nm CMOS, the designed transmitter prototype achieves a peak data rate of 32 Gb/s and an energy efficiency of 2.1 mW/Gb/s.

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KW - feed-forward equalization

KW - level-mismatch correction

KW - transmitter

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JO - IEEE Microwave and Wireless Components Letters

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ER -

A 32-Gb/s C2C-DAC-Based PAM-4 Wireline Transmitter with Two-Tap Feed-Forward Equalization and Level-Mismatch Correction in 28-nm CMOS

Abstract

UN SDGs

Keywords

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