TY - GEN
T1 - A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface
AU - Cho, Wei Han
AU - Li, Yilei
AU - Kim, Yanghyo
AU - Huang, Po Tsang
AU - Du, Yuan
AU - Lee, Sheau Jiung
AU - Chang, Mau Chung Frank
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/11/25
Y1 - 2015/11/25
N2 - This paper presents a novel self-equalized and skewless frequency-division multiplexing memory interface. To prove its feasibility, we have realized a 5-band QPSK transceiver in 40 nm CMOS to transmit up to 4 Gb/s through 10 orthogonal communication channels (each with 400 Mb/s) via on-chip TSV emulator with effective loading of 1 pF or 5-cm FR-4 PCB trace. With differential current-mode signaling, the transceiver consumes only 5.4 mW and takes only 80×100 μm2. A real-time flexible BER testing platform is established to prove that the BER of the transceiver is less than 10-12.
AB - This paper presents a novel self-equalized and skewless frequency-division multiplexing memory interface. To prove its feasibility, we have realized a 5-band QPSK transceiver in 40 nm CMOS to transmit up to 4 Gb/s through 10 orthogonal communication channels (each with 400 Mb/s) via on-chip TSV emulator with effective loading of 1 pF or 5-cm FR-4 PCB trace. With differential current-mode signaling, the transceiver consumes only 5.4 mW and takes only 80×100 μm2. A real-time flexible BER testing platform is established to prove that the BER of the transceiver is less than 10-12.
KW - BER testing platform
KW - RF interconnects
KW - current-mode Schmitt trigger
KW - multi-band transceiver
UR - http://www.scopus.com/inward/record.url?scp=84959201204&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84959201204&partnerID=8YFLogxK
U2 - 10.1109/CICC.2015.7338373
DO - 10.1109/CICC.2015.7338373
M3 - Conference contribution
AN - SCOPUS:84959201204
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - 2015 IEEE Custom Integrated Circuits Conference, CICC 2015
T2 - IEEE Custom Integrated Circuits Conference, CICC 2015
Y2 - 28 September 2015 through 30 September 2015
ER -