TY - GEN
T1 - A methodology for timing model characterization for statistical static timing analysis
AU - Feng, Zhuo
AU - Li, Peng
PY - 2007
Y1 - 2007
N2 - While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realization of these techniques heavily depends on the availability of timing models that feed the statistical timing analysis engine. To target at this critical but less explored territory, in this paper, we present numerical and statistical modeling techniques that are suitable for the underlying timing model characterization infrastructure of statistical timing analysis. Our techniques are centered around the under-standing that while the widening process variability calls for accurate non-first-order timing models, their deployment requires well-controlled characterization techniques to cope with the complexity and scalability. We present a methodology by which timing variabilities in interconnects and nonlinear gates are translated efficiently into quadratic timing models suitable for accurate statistical timing analysis. Specific parameter reduction techniques are developed to control the characterization cost that is a function of number of variation sources. The proposed techniques are extensively demonstrated under the context of logic stage timing characterization involving interactions between logic gates and interconnects.
AB - While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realization of these techniques heavily depends on the availability of timing models that feed the statistical timing analysis engine. To target at this critical but less explored territory, in this paper, we present numerical and statistical modeling techniques that are suitable for the underlying timing model characterization infrastructure of statistical timing analysis. Our techniques are centered around the under-standing that while the widening process variability calls for accurate non-first-order timing models, their deployment requires well-controlled characterization techniques to cope with the complexity and scalability. We present a methodology by which timing variabilities in interconnects and nonlinear gates are translated efficiently into quadratic timing models suitable for accurate statistical timing analysis. Specific parameter reduction techniques are developed to control the characterization cost that is a function of number of variation sources. The proposed techniques are extensively demonstrated under the context of logic stage timing characterization involving interactions between logic gates and interconnects.
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U2 - 10.1109/ICCAD.2007.4397351
DO - 10.1109/ICCAD.2007.4397351
M3 - Conference contribution
AN - SCOPUS:50249111053
SN - 1424413826
SN - 9781424413829
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 725
EP - 729
BT - 2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD
T2 - 2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD
Y2 - 4 November 2007 through 8 November 2007
ER -