TY - JOUR
T1 - A Multilevel Spectral Framework for Scalable Vectorless Power/Thermal Integrity Verification
AU - Zhao, Zhiqiang
AU - Feng, Zhuo
N1 - Publisher Copyright:
© 2022 Association for Computing Machinery.
PY - 2022/12/10
Y1 - 2022/12/10
N2 - Vectorless integrity verification is becoming increasingly critical to the robust design of nanoscale integrated circuits. This article introduces a general vectorless integrity verification framework that allows computing the worst-case voltage drops or temperature (gradient) distributions across the entire chip under a set of local and global workload (power density) constraints. To address the computational challenges introduced by the large power grids and three-dimensional mesh-structured thermal grids, we propose a novel spectral approach for highly scalable vectorless verification of large chip designs by leveraging a hierarchy of almost linear-sized spectral sparsifiers of input grids that can well retain effective resistances between nodes. As a result, the vectorless integrity verification solution obtained on coarse-level problems can effectively help compute the solution of the original problem. Our approach is based on emerging spectral graph theory and graph signal processing techniques, which consists of a graph topology sparsification and graph coarsening phase, an edge weight scaling phase, as well as a solution refinement procedure. Extensive experimental results show that the proposed vectorless verification framework can efficiently and accurately obtain worst-case scenarios in even very large designs.
AB - Vectorless integrity verification is becoming increasingly critical to the robust design of nanoscale integrated circuits. This article introduces a general vectorless integrity verification framework that allows computing the worst-case voltage drops or temperature (gradient) distributions across the entire chip under a set of local and global workload (power density) constraints. To address the computational challenges introduced by the large power grids and three-dimensional mesh-structured thermal grids, we propose a novel spectral approach for highly scalable vectorless verification of large chip designs by leveraging a hierarchy of almost linear-sized spectral sparsifiers of input grids that can well retain effective resistances between nodes. As a result, the vectorless integrity verification solution obtained on coarse-level problems can effectively help compute the solution of the original problem. Our approach is based on emerging spectral graph theory and graph signal processing techniques, which consists of a graph topology sparsification and graph coarsening phase, an edge weight scaling phase, as well as a solution refinement procedure. Extensive experimental results show that the proposed vectorless verification framework can efficiently and accurately obtain worst-case scenarios in even very large designs.
KW - Vectorless integrity verification
KW - graph signal processing
KW - spectral graph coarsening
KW - spectral graph theory
UR - http://www.scopus.com/inward/record.url?scp=85147258636&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85147258636&partnerID=8YFLogxK
U2 - 10.1145/3529534
DO - 10.1145/3529534
M3 - Article
AN - SCOPUS:85147258636
SN - 1084-4309
VL - 28
JO - ACM Transactions on Design Automation of Electronic Systems
JF - ACM Transactions on Design Automation of Electronic Systems
IS - 1
M1 - 3529534
ER -