TY - GEN
T1 - Checkpoints and continuations instead of nested transactions
AU - Koskinen, Eric
AU - Herlihy, Maurice
PY - 2008
Y1 - 2008
N2 - We present a mechanism for partially aborting transactions through the use of data structure checkpoints and control-flow continuations. In particular, we show that boosted transactions [9] already have built-in restoration points and afford a simple, efficient implementation. Our mechanism is far simpler than previous work, which relied on complex nesting schemes to establish checkpoints. We demonstrate syntactic advantages and we quantify the overhead of checkpoints and explore several examples, illustrating the utility of partially aborting transactions. We additionally present a novel queue-based spin lock which allows threads to timeout and differ in priority. Unlike the known lock due to Craig [5], our lock is more efficient for priority schemes of few levels.
AB - We present a mechanism for partially aborting transactions through the use of data structure checkpoints and control-flow continuations. In particular, we show that boosted transactions [9] already have built-in restoration points and afford a simple, efficient implementation. Our mechanism is far simpler than previous work, which relied on complex nesting schemes to establish checkpoints. We demonstrate syntactic advantages and we quantify the overhead of checkpoints and explore several examples, illustrating the utility of partially aborting transactions. We additionally present a novel queue-based spin lock which allows threads to timeout and differ in priority. Unlike the known lock due to Craig [5], our lock is more efficient for priority schemes of few levels.
KW - Boosting
KW - Checkpoints
KW - Concurrency
KW - Continuations
KW - Parallel programming
KW - Transactional memory
UR - http://www.scopus.com/inward/record.url?scp=57349187155&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=57349187155&partnerID=8YFLogxK
U2 - 10.1145/1378533.1378563
DO - 10.1145/1378533.1378563
M3 - Conference contribution
AN - SCOPUS:57349187155
SN - 9781595939739
T3 - Annual ACM Symposium on Parallelism in Algorithms and Architectures
SP - 160
EP - 168
BT - SPAA'08 - Proceedings of the 20th Annual Symposium on Parallelism in Algorithms and Architectures
T2 - 20th ACM Symposium on Parallelism in Algorithms and Architectures, SPAA'08
Y2 - 14 June 2008 through 16 June 2008
ER -