Combinatorial algorithms for fast clock mesh optimization

Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

35 Scopus citations

Abstract

We present a fast and efficient combinatorial algorithm to simultaneously identify the candidate locations as well as the sizes of the buffers driving a clock mesh. Due to the high redundancy, a mesh architecture offers high tolerance towards variation in the clock skew. However, such a redundancy comes at the expense of mesh wire length and power dissipation. Based on survivable network theory, we formulate the problem to reduce the clock mesh by retaining only those edges that are critical to maintain redundancy. Such a formulation offers designer the option to trade-off between power and tolerance to process variations. Experimental results indicate that our techniques can result in power savings up to 28% with less than 4% delay penalty.

Original languageEnglish
Title of host publicationProceedings of the 2006 International Conference on Computer-Aided Design, ICCAD
Pages563-567
Number of pages5
DOIs
StatePublished - 2006
Event2006 International Conference on Computer-Aided Design, ICCAD - San Jose, CA, United States
Duration: 5 Nov 20069 Nov 2006

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Conference

Conference2006 International Conference on Computer-Aided Design, ICCAD
Country/TerritoryUnited States
CitySan Jose, CA
Period5/11/069/11/06

Fingerprint

Dive into the research topics of 'Combinatorial algorithms for fast clock mesh optimization'. Together they form a unique fingerprint.

Cite this