TY - GEN
T1 - Contrastive Graph Convolutional Networks for Hardware Trojan Detection in Third Party IP Cores
AU - Muralidhar, Nikhil
AU - Zubair, Abdullah
AU - Weidler, Nathanael
AU - Gerdes, Ryan
AU - Ramakrishnan, Naren
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - The availability of wide-ranging third-party intellectual property (3PIP) cores enables integrated circuit (IC) designers to focus on designing high-level features in ASICs/SoCs. The massive proliferation of ICs brings with it an increased number of bad actors seeking to exploit those circuits for various nefarious reasons. This is not surprising as integrated circuits affect every aspect of society. Thus, malicious logic (Hardware Trojans, HT) being surreptitiously injected by untrusted vendors into 3PIP cores used in IC design is an ever present threat. In this paper, we explore methods for identification of trigger-based HT in designs containing synthesizable IP cores without a golden model. Specifically, we develop methods to detect hardware trojans by detecting triggers embedded in ICs purely based on netlists acquired from the vendor. We propose GATE-Net, a deep learning model based on graph-convolutional networks (GCN) trained using supervised contrastive learning, for flagging designs containing randomly-inserted triggers using only the corresponding netlist. Our proposed architecture achieves significant improvements over state-of-the-art learning models yielding an average 46.99% improvement in detection performance for combinatorial triggers and 21.91% improvement for sequential triggers across a variety of circuit types. Through rigorous experimentation, qualitative and quantitative performance evaluations, we demonstrate effectiveness of GATE-Net and the supervised contrastive training of GATE-Net for HT detection. Code and data are publicly available∗.
AB - The availability of wide-ranging third-party intellectual property (3PIP) cores enables integrated circuit (IC) designers to focus on designing high-level features in ASICs/SoCs. The massive proliferation of ICs brings with it an increased number of bad actors seeking to exploit those circuits for various nefarious reasons. This is not surprising as integrated circuits affect every aspect of society. Thus, malicious logic (Hardware Trojans, HT) being surreptitiously injected by untrusted vendors into 3PIP cores used in IC design is an ever present threat. In this paper, we explore methods for identification of trigger-based HT in designs containing synthesizable IP cores without a golden model. Specifically, we develop methods to detect hardware trojans by detecting triggers embedded in ICs purely based on netlists acquired from the vendor. We propose GATE-Net, a deep learning model based on graph-convolutional networks (GCN) trained using supervised contrastive learning, for flagging designs containing randomly-inserted triggers using only the corresponding netlist. Our proposed architecture achieves significant improvements over state-of-the-art learning models yielding an average 46.99% improvement in detection performance for combinatorial triggers and 21.91% improvement for sequential triggers across a variety of circuit types. Through rigorous experimentation, qualitative and quantitative performance evaluations, we demonstrate effectiveness of GATE-Net and the supervised contrastive training of GATE-Net for HT detection. Code and data are publicly available∗.
KW - contrastive learning
KW - deep learning
KW - graph convolutional network
KW - hardware trojan
KW - machine learning
UR - http://www.scopus.com/inward/record.url?scp=85121306428&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85121306428&partnerID=8YFLogxK
U2 - 10.1109/HOST49136.2021.9702276
DO - 10.1109/HOST49136.2021.9702276
M3 - Conference contribution
AN - SCOPUS:85121306428
T3 - Proceedings of the 2021 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2021
SP - 181
EP - 191
BT - Proceedings of the 2021 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2021
T2 - 2021 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2021
Y2 - 13 December 2021 through 14 December 2021
ER -