D-band frequency synthesis using a U-band PLL and frequency tripler in 65nm CMOS technology

Adrian Tang, David Murphy, Gabriel Virbila, Frank Hsiao, Sai Wang Tam, Hsing Ting Yu, Hsieh Hung Hsieh, Chewn Pu Jou, Yanghyo Kim, Alden Wong, Alex Wong, Yi Cheng Wu, Mau Chung Frank Chang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

This paper presents a digitally controlled frequency synthesizer in 65nm CMOS technology for D-band transceiver applications. The synthesizer uses a low frequency U Band (44-48 GHz) phase-locked loop to track a 50 MHz reference and then employs an injection locked frequency tripler (ILFT) to provide output that can be tuned between 130 and 133 GHz. The proposed D-band synthesizer offers a directly measured phase noise of 82.5 dBc/Hz at 1 MHz offset from the carrier and consumes 92mW of power. The entire syntheszier occupies 0.68mm2 of silicon area.

Original languageEnglish
Title of host publicationIMS 2012 - 2012 IEEE MTT-S International Microwave Symposium
DOIs
StatePublished - 2012
Event2012 IEEE MTT-S International Microwave Symposium, IMS 2012 - Montreal, QC, Canada
Duration: 17 Jun 201222 Jun 2012

Publication series

NameIEEE MTT-S International Microwave Symposium Digest
ISSN (Print)0149-645X

Conference

Conference2012 IEEE MTT-S International Microwave Symposium, IMS 2012
Country/TerritoryCanada
CityMontreal, QC
Period17/06/1222/06/12

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