TY - JOUR
T1 - Do chip size limits exist for DCA?
AU - Schubert, Andreas
AU - Dudek, Rainer
AU - Leutenbauer, Rudolf
AU - Döring, Ralf
AU - Kloeser, Joachim
AU - Oppermann, H.
AU - Michel, Bernd
AU - Reichl, Herbert
AU - Baldwin, Daniel F.
AU - Qu, Jianmin
AU - Sitaraman, Suresh K.
AU - Swaminathan, M.
AU - Wong, C. P.
AU - Tummala, Rao
PY - 1999
Y1 - 1999
N2 - Solder joints, the most widely used flip chip on board (FCOB) interconnects, have a relatively low structural compliance due to the large thermal expansion mismatch between silicon die and the organic substrate. The coefficient of thermal expansion (CTE) of the printed wiring board (PWB) is almost an order of magnitude greater than that of the integrated circuit (IC). Under operating and testing conditions, this mismatch subjects the solder joints to large creep strains and leads to early failure of the solder connections [1]-[3]. The reliability of such flip chip structures can be enhanced by applying an epoxy-based underfill between the chip and the substrate, encapsulating the solder joints. This material, once cured, mechanically couples the IC and substrate together to locally constrain the CTE mismatch. However, the effects of CTE mismatch are assumed to become more severe with increasing chip size. Even with the addition of an underfill material, it has been supposed that there are limits on the chip size used in flip chip applications [4].
AB - Solder joints, the most widely used flip chip on board (FCOB) interconnects, have a relatively low structural compliance due to the large thermal expansion mismatch between silicon die and the organic substrate. The coefficient of thermal expansion (CTE) of the printed wiring board (PWB) is almost an order of magnitude greater than that of the integrated circuit (IC). Under operating and testing conditions, this mismatch subjects the solder joints to large creep strains and leads to early failure of the solder connections [1]-[3]. The reliability of such flip chip structures can be enhanced by applying an epoxy-based underfill between the chip and the substrate, encapsulating the solder joints. This material, once cured, mechanically couples the IC and substrate together to locally constrain the CTE mismatch. However, the effects of CTE mismatch are assumed to become more severe with increasing chip size. Even with the addition of an underfill material, it has been supposed that there are limits on the chip size used in flip chip applications [4].
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M3 - Article
AN - SCOPUS:33748091703
SN - 1521-334X
VL - 22
SP - 249
JO - IEEE Transactions on Electronics Packaging Manufacturing
JF - IEEE Transactions on Electronics Packaging Manufacturing
IS - 4
ER -