TY - GEN
T1 - Efficient checking of power delivery integrity for power gating
AU - Zeng, Zhiyu
AU - Feng, Zhuo
AU - Li, Peng
PY - 2011
Y1 - 2011
N2 - Multi-core architecture has emerged as the primary architectural choice to achieve power-efficient computing in microprocessors and SoCs. Power gating is indispensable for system power and thermal management and well suited for multi-core architectures. However, checking the power integrity (such as electromigration and voltage drop) of large gated power delivery networks (PDNs) presents a significant challenge due to the sheer die-package network complexity and the existence of an extremely large number of possible gating and operation configurations. We propose a simulation-based checking methodology that encompasses a comprehensive set of essential checking tasks. We tackle the challenges brought by the large checking space by developing strategies that efficiently identify top-ranked worst-case operating conditions, which are sequentially analyzed through a well-controlled number of full simulations for fidelity. We demonstrate the superior performance of the proposed approach on large power gating checking problems that are completely intractable to brute-force methods.
AB - Multi-core architecture has emerged as the primary architectural choice to achieve power-efficient computing in microprocessors and SoCs. Power gating is indispensable for system power and thermal management and well suited for multi-core architectures. However, checking the power integrity (such as electromigration and voltage drop) of large gated power delivery networks (PDNs) presents a significant challenge due to the sheer die-package network complexity and the existence of an extremely large number of possible gating and operation configurations. We propose a simulation-based checking methodology that encompasses a comprehensive set of essential checking tasks. We tackle the challenges brought by the large checking space by developing strategies that efficiently identify top-ranked worst-case operating conditions, which are sequentially analyzed through a well-controlled number of full simulations for fidelity. We demonstrate the superior performance of the proposed approach on large power gating checking problems that are completely intractable to brute-force methods.
UR - http://www.scopus.com/inward/record.url?scp=79959213941&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79959213941&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2011.5770800
DO - 10.1109/ISQED.2011.5770800
M3 - Conference contribution
AN - SCOPUS:79959213941
SN - 9781612849140
T3 - Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
SP - 663
EP - 670
BT - Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
T2 - 12th International Symposium on Quality Electronic Design, ISQED 2011
Y2 - 14 March 2011 through 16 March 2011
ER -