Efficient checking of power delivery integrity for power gating

Zhiyu Zeng, Zhuo Feng, Peng Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

Multi-core architecture has emerged as the primary architectural choice to achieve power-efficient computing in microprocessors and SoCs. Power gating is indispensable for system power and thermal management and well suited for multi-core architectures. However, checking the power integrity (such as electromigration and voltage drop) of large gated power delivery networks (PDNs) presents a significant challenge due to the sheer die-package network complexity and the existence of an extremely large number of possible gating and operation configurations. We propose a simulation-based checking methodology that encompasses a comprehensive set of essential checking tasks. We tackle the challenges brought by the large checking space by developing strategies that efficiently identify top-ranked worst-case operating conditions, which are sequentially analyzed through a well-controlled number of full simulations for fidelity. We demonstrate the superior performance of the proposed approach on large power gating checking problems that are completely intractable to brute-force methods.

Original languageEnglish
Title of host publicationProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
Pages663-670
Number of pages8
DOIs
StatePublished - 2011
Event12th International Symposium on Quality Electronic Design, ISQED 2011 - Santa Clara, CA, United States
Duration: 14 Mar 201116 Mar 2011

Publication series

NameProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011

Conference

Conference12th International Symposium on Quality Electronic Design, ISQED 2011
Country/TerritoryUnited States
CitySanta Clara, CA
Period14/03/1116/03/11

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