TY - GEN
T1 - Efficient model update for general link-insertion networks
AU - Feng, Zhuo
AU - Li, Peng
AU - Hu, Jiang
PY - 2006
Y1 - 2006
N2 - Link insertion has been proposed as a means of incremental design to improve performance robustness of linear passive networks. In clock network design, links can be inserted between subnetworks to reduce the variability of clock skews introduced by process and environmental fluctuations, thereby improving the network's immunity to PVT variations. Under these scenarios, it is desired to incrementally compute a reduced-order model for the updated network in order to efficiently evaluate the effectiveness of link insertions. In this paper, we present an efficient model update scheme for general link-insertion networks. By updating the Krylov projection subspace used in model order reduction, the proposed scheme can efficiently compute a reduced-order model for the network with inserted links. More generally, we extend the proposed approach to consider the merging of a (small) multiple-input linear network with a much larger network. We demonstrate the usage of the proposed technique for clock networks and general RLC circuits with an arbitrary number of link insertions as well as the more general case where the inserted links are in the form of a linear network.
AB - Link insertion has been proposed as a means of incremental design to improve performance robustness of linear passive networks. In clock network design, links can be inserted between subnetworks to reduce the variability of clock skews introduced by process and environmental fluctuations, thereby improving the network's immunity to PVT variations. Under these scenarios, it is desired to incrementally compute a reduced-order model for the updated network in order to efficiently evaluate the effectiveness of link insertions. In this paper, we present an efficient model update scheme for general link-insertion networks. By updating the Krylov projection subspace used in model order reduction, the proposed scheme can efficiently compute a reduced-order model for the network with inserted links. More generally, we extend the proposed approach to consider the merging of a (small) multiple-input linear network with a much larger network. We demonstrate the usage of the proposed technique for clock networks and general RLC circuits with an arbitrary number of link insertions as well as the more general case where the inserted links are in the form of a linear network.
UR - http://www.scopus.com/inward/record.url?scp=62949162311&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=62949162311&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2006.55
DO - 10.1109/ISQED.2006.55
M3 - Conference contribution
AN - SCOPUS:62949162311
SN - 0769525237
SN - 9780769525235
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 43
EP - 50
BT - Proceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006
T2 - 7th International Symposium on Quality Electronic Design, ISQED 2006
Y2 - 27 March 2006 through 29 March 2006
ER -