TY - GEN
T1 - Fast second-order statistical static timing analysis using parameter dimension reduction
AU - Feng, Zhuo
AU - Li, Peng
AU - Zhan, Yaping
PY - 2007
Y1 - 2007
N2 - The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of timing analysis, the need for combating process variations has sparkled a growing body of statistical static timing analysis (SSTA) techniques. While first-order SSTA techniques enjoy good runtime efficiency desired for tackling large industrial designs, more accurate second-order SSTA techniques have been proposed to improve the analysis accuracy, but at the cost of high computational complexity. Although many sources of variations may impact the circuit performance, considering a large number of inter-die and intra-die variations in the traditional SSTA analysis is very challenging. In this paper, we address the analysis complexity brought by high parameter dimensionality in static timing analysis and propose an accurate yet fast second-order SSTA algorithm based upon novel parameter dimension reduction. By developing reduced-rank regression based parameter reduction algorithms within block-based SSTA flow, we demonstrate that accurate second order SSTA analysis can be extended to a much higher parameter dimensionality than what is possible before. Our experimental results have shown that the proposed parameter reduction can achieve up to 10X parameter dimension reduction and lead to significantly improved second-order SSTA analysis under a large set of process variations.
AB - The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of timing analysis, the need for combating process variations has sparkled a growing body of statistical static timing analysis (SSTA) techniques. While first-order SSTA techniques enjoy good runtime efficiency desired for tackling large industrial designs, more accurate second-order SSTA techniques have been proposed to improve the analysis accuracy, but at the cost of high computational complexity. Although many sources of variations may impact the circuit performance, considering a large number of inter-die and intra-die variations in the traditional SSTA analysis is very challenging. In this paper, we address the analysis complexity brought by high parameter dimensionality in static timing analysis and propose an accurate yet fast second-order SSTA algorithm based upon novel parameter dimension reduction. By developing reduced-rank regression based parameter reduction algorithms within block-based SSTA flow, we demonstrate that accurate second order SSTA analysis can be extended to a much higher parameter dimensionality than what is possible before. Our experimental results have shown that the proposed parameter reduction can achieve up to 10X parameter dimension reduction and lead to significantly improved second-order SSTA analysis under a large set of process variations.
KW - Parameter dimension reduction
KW - Process variation
KW - Statistical timing
UR - http://www.scopus.com/inward/record.url?scp=34547308113&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34547308113&partnerID=8YFLogxK
U2 - 10.1109/DAC.2007.375161
DO - 10.1109/DAC.2007.375161
M3 - Conference contribution
AN - SCOPUS:34547308113
SN - 1595936270
SN - 9781595936271
T3 - Proceedings - Design Automation Conference
SP - 244
EP - 249
BT - 2007 44th ACM/IEEE Design Automation Conference, DAC'07
T2 - 2007 44th ACM/IEEE Design Automation Conference, DAC'07
Y2 - 4 June 2007 through 8 June 2007
ER -