TY - GEN
T1 - Graph sparsification approaches to scalable integrated circuit modeling and simulations
AU - Feng, Zhuo
AU - Zhao, Xueqian
AU - Han, Lengfei
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/1/23
Y1 - 2014/1/23
N2 - Unlike traditional fast SPICE simulation techniques that rely on a variety of approximation approaches to trade off simulation accuracy for greater speed, SPICE-accurate integrated circuit (IC) simulations can truthfully predict circuit electrical behaviors, and therefore become indispensable for verification of large IC designs. Post-layout SPICE-accurate simulation should be able to encapsulate multi-million or even multi-billion devices that are coupled through complex parasitics and become an essential procedure for verification of nowadays nano-scale IC designs. Although many efficient numerical methods have been developed and adopted in the state-of-the-art SPICE-accurate circuit simulators for solving large sparse matrices involved in IC simulations, existing simulators may not be capable of handling extremely large-scale post-layout ICs in that the computation and memory cost can increase exponentially with the increase of circuit sizes and parasitics components. This paper introduces our recent effort in developing 'truly scalable' SPICE-accurate nonlinear circuit simulation methods that can scale comfortably with extremely large-scale post-layout IC designs without sacrificing accuracy.
AB - Unlike traditional fast SPICE simulation techniques that rely on a variety of approximation approaches to trade off simulation accuracy for greater speed, SPICE-accurate integrated circuit (IC) simulations can truthfully predict circuit electrical behaviors, and therefore become indispensable for verification of large IC designs. Post-layout SPICE-accurate simulation should be able to encapsulate multi-million or even multi-billion devices that are coupled through complex parasitics and become an essential procedure for verification of nowadays nano-scale IC designs. Although many efficient numerical methods have been developed and adopted in the state-of-the-art SPICE-accurate circuit simulators for solving large sparse matrices involved in IC simulations, existing simulators may not be capable of handling extremely large-scale post-layout ICs in that the computation and memory cost can increase exponentially with the increase of circuit sizes and parasitics components. This paper introduces our recent effort in developing 'truly scalable' SPICE-accurate nonlinear circuit simulation methods that can scale comfortably with extremely large-scale post-layout IC designs without sacrificing accuracy.
UR - http://www.scopus.com/inward/record.url?scp=84946689766&partnerID=8YFLogxK
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U2 - 10.1109/ICSICT.2014.7021195
DO - 10.1109/ICSICT.2014.7021195
M3 - Conference contribution
AN - SCOPUS:84946689766
T3 - Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014
BT - Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014
A2 - Zhou, Jia
A2 - Tang, Ting-Ao
T2 - 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014
Y2 - 28 October 2014 through 31 October 2014
ER -