Influence of die size on the magnitude of thermomechanical stresses in flip chips directly attached to printed wiring board

C. A. Le Gall, J. Qu, D. L. McDowell

Research output: Contribution to journalArticlepeer-review

13 Scopus citations

Abstract

Flip chip interconnection technology has recently been extended to direct chip attach (DCA) to organic printed wiring boards (PWBs). However, the coefficient of thermal expansion (CTE) of the PWB is almost an order of magnitude greater than that of the silicon die; under processing or operating conditions, this mismatch subjects the solder joints to cyclic stresses, which may result in mechanical fatigue failure of the solder connections. Such CTE mismatch-induced stresses, manifested by the increasing die size and temperature excursions, have posed a great challenge to the thermomechanical reliability of flip-chip DCA packages. To prevent premature thermomechanical failure and to ensure the reliability of a DCA package, the thermomechanical stresses caused by the CTE mismatch, which is the driving force to failure, must be understood. Furthermore, design and processing technologies must be developed to minimize such stresses. In this paper, a general methodology is developed to conduct stress analysis in flip-chip DCA with underfill encapsulation using the finite element method. In particular, the effects of die size on the stress fields are addressed. It is shown that the nature of stress fields in underfilled flip chips is fundamentally different from the stress fields of other surface mount assemblies. The distance to neutral point (DNP) is no longer a dominant factor in determining the magnitude of the stresses in underfilled flip-chip packages. Consequently, as far as the stresses are concerned, the die size is not a limiting factor.

Original languageEnglish
Pages (from-to)1663-1670
Number of pages8
JournalAmerican Society of Mechanical Engineers, EEP
Volume19
Issue number2
StatePublished - 1997

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