TY - GEN
T1 - Late Breaking Results
T2 - 2026 Design, Automation and Test in Europe Conference, DATE 2026
AU - Stein, Daniel
AU - Huang, Shaoyi
AU - Drechsler, Rolf
AU - Li, Bing
AU - Zhang, Grace Li
N1 - Publisher Copyright:
© 2026 EDAA.
PY - 2026
Y1 - 2026
N2 - Neural networks have been successfully applied in various resource-constrained edge devices, where usually central processing units (CPUs) instead of graphics processing units exist due to limited power availability. State-of-the-art research still focuses on efficiently executing enormous numbers of multiply-accumulate (MAC) operations. However, CPUs themselves are not good at executing such mathematical operations on a large scale, since they are more suited to execute control flow logic, i.e., computer algorithms. To enhance the computation efficiency of neural networks on CPUs, in this paper, we propose to convert them into logic flows for execution. Specifically, neural networks are first converted into equivalent decision trees, from which decision paths with constant leaves are then selected and compressed into logic flows. Such logic flows consist of if and else structures and a reduced number of MAC operations. Experimental results demonstrate that the latency can be reduced by up to 14.9 % on a simulated RISC-V CPU without any accuracy degradation. - The code is open source at https://github.com/TUDa-HWAI/NN2Logic
AB - Neural networks have been successfully applied in various resource-constrained edge devices, where usually central processing units (CPUs) instead of graphics processing units exist due to limited power availability. State-of-the-art research still focuses on efficiently executing enormous numbers of multiply-accumulate (MAC) operations. However, CPUs themselves are not good at executing such mathematical operations on a large scale, since they are more suited to execute control flow logic, i.e., computer algorithms. To enhance the computation efficiency of neural networks on CPUs, in this paper, we propose to convert them into logic flows for execution. Specifically, neural networks are first converted into equivalent decision trees, from which decision paths with constant leaves are then selected and compressed into logic flows. Such logic flows consist of if and else structures and a reduced number of MAC operations. Experimental results demonstrate that the latency can be reduced by up to 14.9 % on a simulated RISC-V CPU without any accuracy degradation. - The code is open source at https://github.com/TUDa-HWAI/NN2Logic
KW - Edge computing
KW - Logic flows of neural networks
KW - Neural network on CPUs
UR - https://www.scopus.com/pages/publications/105041963489
UR - https://www.scopus.com/pages/publications/105041963489#tab=citedBy
U2 - 10.23919/DATE69613.2026.11539745
DO - 10.23919/DATE69613.2026.11539745
M3 - Conference contribution
AN - SCOPUS:105041963489
T3 - Proceedings -Design, Automation and Test in Europe, DATE
BT - 2026 Design, Automation and Test in Europe Conference, DATE 2026 - Proceedings
Y2 - 20 April 2026 through 22 April 2026
ER -