TY - GEN
T1 - Multi-packaging-level thermal modeling technique for silicon chip transistors
AU - Suwa, Tohru
AU - Hadim, Hamid
PY - 2010
Y1 - 2010
N2 - Although thermal performance is always a critical issue in electronic packaging design at every packaging level, there is a significant lack of reliable and efficient thermal modeling and analysis techniques at the silicon chip level. With millions of transistor gates acting as heat sources, accurate thermal modeling and analysis at micrometer level has not been possible using conventional techniques. For the present study, an efficient and accurate multi-level thermal modeling and analysis technique integrating transistor level into silicon chip level has been developed. The technique combines finite element analysis sub-modeling and superposition methods for more efficient modeling and simulation. Detailed temperature distribution caused by a single heat source is obtained using the finite element sub-modeling technique, while the temperature rise distribution caused by multiple heat sources is obtained using the superposition method. Using the proposed thermal modeling methodology, one case of finite element analysis with a single heat source is sufficient for modeling a silicon chip with millions of transistors acting as heat sources. When the whole package is modeled in the finite element analysis, the effect of the package is also included in the superposition results, which makes possible to model over one million transistors in a silicon chip. No present methodologies for existing silicon chip thermal modeling techniques have been able to model such a large number of transistors. The capabilities of the proposed methodology are demonstrated through a case study involving thermal modeling and analysis of a microprocessor chip.
AB - Although thermal performance is always a critical issue in electronic packaging design at every packaging level, there is a significant lack of reliable and efficient thermal modeling and analysis techniques at the silicon chip level. With millions of transistor gates acting as heat sources, accurate thermal modeling and analysis at micrometer level has not been possible using conventional techniques. For the present study, an efficient and accurate multi-level thermal modeling and analysis technique integrating transistor level into silicon chip level has been developed. The technique combines finite element analysis sub-modeling and superposition methods for more efficient modeling and simulation. Detailed temperature distribution caused by a single heat source is obtained using the finite element sub-modeling technique, while the temperature rise distribution caused by multiple heat sources is obtained using the superposition method. Using the proposed thermal modeling methodology, one case of finite element analysis with a single heat source is sufficient for modeling a silicon chip with millions of transistors acting as heat sources. When the whole package is modeled in the finite element analysis, the effect of the package is also included in the superposition results, which makes possible to model over one million transistors in a silicon chip. No present methodologies for existing silicon chip thermal modeling techniques have been able to model such a large number of transistors. The capabilities of the proposed methodology are demonstrated through a case study involving thermal modeling and analysis of a microprocessor chip.
KW - Integrated circuit (IC)
KW - Multi-level modeling
KW - Silicon chip
KW - Thermal modeling
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U2 - 10.1115/IMECE2009-11815
DO - 10.1115/IMECE2009-11815
M3 - Conference contribution
AN - SCOPUS:77954257909
SN - 9780791843826
T3 - ASME International Mechanical Engineering Congress and Exposition, Proceedings
SP - 1365
EP - 1372
BT - Proceedings of the ASME International Mechanical Engineering Congress and Exposition 2009, IMECE 2009
T2 - ASME 2009 International Mechanical Engineering Congress and Exposition, IMECE2009
Y2 - 13 November 2009 through 19 November 2009
ER -