TY - GEN
T1 - Multidisciplinary heat generating logic block placement optimization using genetic algorithm
AU - Suwa, Tohru
AU - Hadim, Hamid
PY - 2007
Y1 - 2007
N2 - A multidisciplinary optimization methodology for placement of heat generating logic blocks on integrated circuit chips is presented. The methodology includes thermal and wiring length criteria, which are optimized simultaneously using the genetic algorithm. An effective thermal performance prediction methodology based on a superposition method is used to calculate the temperature distribution on a silicon chip due to multiple heat generating logic blocks. Using the superposition method, the predicted temperature distribution in the silicon chip is obtained in a much shorter time than with a detailed finite element model and with comparable accuracy. The main advantage of the present multi-disciplinary design and optimization methodology is its ability to handle multiple design objectives simultaneously for optimized placement of heat generating logic blocks. To demonstrate its capabilities, the present methodology is applied to benchmark cases involving placement optimization of multiple heat generating logic blocks on a silicon chip. The results indicate that the maximum temperature on a silicon chip can be reduced by up to 7.5 °C, compared with the case in which only the wiring length is minimized.
AB - A multidisciplinary optimization methodology for placement of heat generating logic blocks on integrated circuit chips is presented. The methodology includes thermal and wiring length criteria, which are optimized simultaneously using the genetic algorithm. An effective thermal performance prediction methodology based on a superposition method is used to calculate the temperature distribution on a silicon chip due to multiple heat generating logic blocks. Using the superposition method, the predicted temperature distribution in the silicon chip is obtained in a much shorter time than with a detailed finite element model and with comparable accuracy. The main advantage of the present multi-disciplinary design and optimization methodology is its ability to handle multiple design objectives simultaneously for optimized placement of heat generating logic blocks. To demonstrate its capabilities, the present methodology is applied to benchmark cases involving placement optimization of multiple heat generating logic blocks on a silicon chip. The results indicate that the maximum temperature on a silicon chip can be reduced by up to 7.5 °C, compared with the case in which only the wiring length is minimized.
KW - Genetic algorithm
KW - Logic block placement
KW - Multidisciplinary optimization
KW - Superposition
KW - Thermal
KW - Wiring length
UR - http://www.scopus.com/inward/record.url?scp=40449089376&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=40449089376&partnerID=8YFLogxK
U2 - 10.1115/IPACK2007-33443
DO - 10.1115/IPACK2007-33443
M3 - Conference contribution
AN - SCOPUS:40449089376
SN - 0791842770
SN - 9780791842775
T3 - 2007 Proceedings of the ASME InterPack Conference, IPACK 2007
SP - 773
EP - 779
BT - 2007 Proceedings of the ASME InterPack Conference, IPACK 2007
T2 - ASME Electronic and Photonics Packaging Division
Y2 - 8 July 2007 through 12 July 2007
ER -