TY - GEN
T1 - Multidisciplinary placement optimization of heat generating semiconductor logic blocks
AU - Suwa, Tohru
AU - Hadim, Hamid
PY - 2009
Y1 - 2009
N2 - A multidisciplinary optimization methodology for placement of heat generating semiconductor logic blocks on integrated circuit chips is presented. The methodology includes thermal and wiring length criteria, which are optimized simultaneously using the genetic algorithm. An effective thermal performance prediction methodology based on a superposition method is used to determine the temperature distribution on a silicon chip due to multiple heat generating logic blocks. Using the superposition method, the predicted temperature distribution in the silicon chip is obtained in much shorter time than with a detailed finite element model and with comparable accuracy. The main advantage of the present multidisciplinary design and optimization methodology is its ability to handle multiple design objectives simultaneously for optimized placement of heat generating logic blocks. Capabilities of the present methodology are demonstrated by applying it to several standard benchmarks. The multidisciplinary logic block placement optimization results indicate that the maximum temperature on a silicon chip can be reduced by up to 7.5°C, compared with the case in which only the wiring length is minimized.
AB - A multidisciplinary optimization methodology for placement of heat generating semiconductor logic blocks on integrated circuit chips is presented. The methodology includes thermal and wiring length criteria, which are optimized simultaneously using the genetic algorithm. An effective thermal performance prediction methodology based on a superposition method is used to determine the temperature distribution on a silicon chip due to multiple heat generating logic blocks. Using the superposition method, the predicted temperature distribution in the silicon chip is obtained in much shorter time than with a detailed finite element model and with comparable accuracy. The main advantage of the present multidisciplinary design and optimization methodology is its ability to handle multiple design objectives simultaneously for optimized placement of heat generating logic blocks. Capabilities of the present methodology are demonstrated by applying it to several standard benchmarks. The multidisciplinary logic block placement optimization results indicate that the maximum temperature on a silicon chip can be reduced by up to 7.5°C, compared with the case in which only the wiring length is minimized.
KW - IC logic block placement
KW - IC thermal design
KW - IC wiring length
KW - Multidisciplinary design optimization
UR - http://www.scopus.com/inward/record.url?scp=70349106006&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70349106006&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:70349106006
SN - 9780791848487
T3 - 2008 Proceedings of the ASME Summer Heat Transfer Conference, HT 2008
SP - 779
EP - 787
BT - 2008 Proceedings of the ASME Summer Heat Transfer Conference, HT 2008
T2 - 2008 ASME Summer Heat Transfer Conference, HT 2008
Y2 - 10 August 2008 through 14 August 2008
ER -