On the ZBDD-based nonenumerative path delay fault coverage calculation

Fatih Kocan, Mehmet H. Gunes

    Research output: Contribution to journalArticlepeer-review

    6 Scopus citations

    Abstract

    We devise one exact and one pessimistic path delay fault (PDF) grading algorithms for combinational circuits. The first algorithm, an extension to the basic grading algorithm of Padmanaban, Michael, and Tragoudas (2003), does not store all of the detected PDFs during the course of grading, and, as a further improvement, it utilizes compressed representation of PDFs. These two techniques yield a space-and-time efficient algorithm. To enable grading of circuits with exponential number of paths, a circuit is first partitioned into a set of subcircuits. The second algorithm efficiently calculates the coverage of partitioned circuits. The former algorithm results in 50%-70% reduction in space and a speedup from 1.6 to 2.48 in ISCAS85 benchmarks. The time complexity of the latter algorithm is O(N2) subset operations per test vector where N is the number of nets in the circuit.

    Original languageEnglish
    Pages (from-to)1137-1143
    Number of pages7
    JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    Volume24
    Issue number7
    DOIs
    StatePublished - Jul 2005

    Keywords

    • Fault grading
    • Path delay fault (PDF)
    • Simulation

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