TY - GEN
T1 - Parallel partitioning based on-chip power distribution network analysis using locality acceleration
AU - Zeng, Zhiyu
AU - Li, Peng
AU - Feng, Zhuo
PY - 2009
Y1 - 2009
N2 - Large VLSI on-chip power distribution networks (PDN) are challenging to analyze due to the sheer network complexity. In this paper, a novel parallel partitioning based PDN analysis approach is presented. We use the boundary circuit responses of each partition to divide the full grid simulation problem into a set of independent sub grid simulation problems. Instead of solving exact boundary circuit responses, a more efficient scheme to provide near exact approximation to the boundary circuit responses by exploiting the spatial locality of the flipchip type power grids is proposed, in which only several small sub power grids need to be solved. This scheme is also used in a block based iterative error reduction process to improve the convergence. Through the analysis of several large power grids, the proposed approach, which can be fully parallelizable, is shown to have great runtime efficiency, fast convergence, and favorable scalability. Our approach can solve a 7.2 million-node power grid in 26 seconds, which is 18 times faster than a state of the art direct solver.
AB - Large VLSI on-chip power distribution networks (PDN) are challenging to analyze due to the sheer network complexity. In this paper, a novel parallel partitioning based PDN analysis approach is presented. We use the boundary circuit responses of each partition to divide the full grid simulation problem into a set of independent sub grid simulation problems. Instead of solving exact boundary circuit responses, a more efficient scheme to provide near exact approximation to the boundary circuit responses by exploiting the spatial locality of the flipchip type power grids is proposed, in which only several small sub power grids need to be solved. This scheme is also used in a block based iterative error reduction process to improve the convergence. Through the analysis of several large power grids, the proposed approach, which can be fully parallelizable, is shown to have great runtime efficiency, fast convergence, and favorable scalability. Our approach can solve a 7.2 million-node power grid in 26 seconds, which is 18 times faster than a state of the art direct solver.
KW - DC analysis
KW - Flip-chip
KW - Locality
KW - On-chip
KW - Parallel
KW - Power distribution network
UR - http://www.scopus.com/inward/record.url?scp=67649656437&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=67649656437&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2009.4810391
DO - 10.1109/ISQED.2009.4810391
M3 - Conference contribution
AN - SCOPUS:67649656437
SN - 9781424429530
T3 - Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009
SP - 776
EP - 781
BT - Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009
T2 - 10th International Symposium on Quality Electronic Design, ISQED 2009
Y2 - 16 March 2009 through 18 March 2009
ER -