TY - JOUR
T1 - Performance-oriented parameter dimension reduction of VLSI circuits
AU - Feng, Zhuo
AU - Li, Peng
PY - 2009/1
Y1 - 2009/1
N2 - To account for the growing process variability in modern VLSI technologies, circuit models parameterized in a multitude of parametric variations are becoming increasingly indispensable in robust circuit design. However, the high parameter dimensionality can introduce significant complexity and may even render variation-aware performance analysis and optimization completely intractable. We present a performance-oriented parameter dimension reduction framework to reduce the modeling complexity associated with high parameter dimensionality. Our framework has a theoretically sound statistical basis, namely, reduced rank regression (RRR) and its various extensions that we have introduced for more practical VLSI circuit modeling. For a variety of VLSI circuits including interconnects and CMOS digital circuits, it is shown that this parameter reduction framework can provide more than one order of magnitude reduction in parameter dimensionality. Such parameter reduction immediately leads to reduced simulation cost in sampling-based performance analysis, and more importantly, highly efficient parameterized sub-circuit models that are instrumental in tackling the complexity of variation-tolerance VLSI system design.
AB - To account for the growing process variability in modern VLSI technologies, circuit models parameterized in a multitude of parametric variations are becoming increasingly indispensable in robust circuit design. However, the high parameter dimensionality can introduce significant complexity and may even render variation-aware performance analysis and optimization completely intractable. We present a performance-oriented parameter dimension reduction framework to reduce the modeling complexity associated with high parameter dimensionality. Our framework has a theoretically sound statistical basis, namely, reduced rank regression (RRR) and its various extensions that we have introduced for more practical VLSI circuit modeling. For a variety of VLSI circuits including interconnects and CMOS digital circuits, it is shown that this parameter reduction framework can provide more than one order of magnitude reduction in parameter dimensionality. Such parameter reduction immediately leads to reduced simulation cost in sampling-based performance analysis, and more importantly, highly efficient parameterized sub-circuit models that are instrumental in tackling the complexity of variation-tolerance VLSI system design.
KW - Circuit simulation
KW - Interconnect modeling
KW - Process variation
KW - Statistical parameter dimension reduction
UR - http://www.scopus.com/inward/record.url?scp=58849152140&partnerID=8YFLogxK
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U2 - 10.1109/TVLSI.2008.2002489
DO - 10.1109/TVLSI.2008.2002489
M3 - Article
AN - SCOPUS:58849152140
SN - 1063-8210
VL - 17
SP - 137
EP - 150
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 1
M1 - 4689320
ER -