Performance-oriented parameter dimension reduction of VLSI circuits

Zhuo Feng, Peng Li

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

To account for the growing process variability in modern VLSI technologies, circuit models parameterized in a multitude of parametric variations are becoming increasingly indispensable in robust circuit design. However, the high parameter dimensionality can introduce significant complexity and may even render variation-aware performance analysis and optimization completely intractable. We present a performance-oriented parameter dimension reduction framework to reduce the modeling complexity associated with high parameter dimensionality. Our framework has a theoretically sound statistical basis, namely, reduced rank regression (RRR) and its various extensions that we have introduced for more practical VLSI circuit modeling. For a variety of VLSI circuits including interconnects and CMOS digital circuits, it is shown that this parameter reduction framework can provide more than one order of magnitude reduction in parameter dimensionality. Such parameter reduction immediately leads to reduced simulation cost in sampling-based performance analysis, and more importantly, highly efficient parameterized sub-circuit models that are instrumental in tackling the complexity of variation-tolerance VLSI system design.

Original languageEnglish
Article number4689320
Pages (from-to)137-150
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume17
Issue number1
DOIs
StatePublished - Jan 2009

Keywords

  • Circuit simulation
  • Interconnect modeling
  • Process variation
  • Statistical parameter dimension reduction

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