Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression

Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models parameterized in a high-dimensional process variation space are desired. However, the high parameter dimensionality, imposed by a large number of variation sources encountered in modern technologies, can introduce significant complexion in circuit analysis and may even render performance variability analysis completely intractable. We address the challenge brought by high-dimensional process variations via a new performance-oriented parameter dimension reduction technique. The basic premise behind our approach is that the dimensionality of performance variability is determined not only by the statistical characteristics of the underlying process variables, but also by the structural information imposed by a given design. Using the powerful reduced rank regression (RRR) and its extension as a vehicle for variability modeling, we are able to systematically identify statistically significant reduced parameter sets and compute not only reduced-parameter but also reduced-parameter-order models that are far more efficient than what was possible before. For a variety of interconnect modeling problems, it is shown that the proposed parameter reduction technique can provide more than one order of magnitude reduction in parameter dimensionality. Such parameter reduction immediately leads to reduced simulation cost in sampling-based performance analysis, and more importantly, highly efficient parameterized interconnect reduced order models. As a general parameter dimension reduction methodology, it is anticipated that the proposed technique is broadly applicable to a variety of statistical circuit modeling problems, thereby offering a useful framework for controlling the complexity of statistical circuit analysis.