Reducing the complexity of VLSI performance variation modeling via parameter dimension reduction

Zhuo Feng, Guo Yu, Peng Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

Parameterized circuit models are desired at various VLSI design stages to account for the increasing process-induced performance variations. However, the large number of process variation sources encountered in modern VLSI technologies often lead to overly complex parameterized models whose generation as well as application is computationally expensive. In this paper, we address this challenge by proposing a general VLSI parameter dimension reduction technique that can produce more compact parameterized models in a compressed set of variation variables. Unlike the widely used principle component analysis (PCA), our new approach is based upon the powerful reduced rank regression (RRR) theory and can lead to a much greater reduction of the parameter space due to the consideration of design-specific structural information. The application of our parameter reduction technique is demonstrated under the context of digital circuit timing simulation and analog macromodeling. Our experimental results have indicated an up to 10X reduction of the parameter space. The application of these compact parameterized models is also outlined under the context of system-level analysis.

Original languageEnglish
Title of host publicationProceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007
Pages737-742
Number of pages6
DOIs
StatePublished - 2007
Event8th International Symposium on Quality Electronic Design, ISQED 2007 - San Jose, CA, United States
Duration: 26 Mar 200728 Mar 2007

Publication series

NameProceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007

Conference

Conference8th International Symposium on Quality Electronic Design, ISQED 2007
Country/TerritoryUnited States
CitySan Jose, CA
Period26/03/0728/03/07

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