TY - JOUR
T1 - SF-SGL
T2 - Solver-Free Spectral Graph Learning From Linear Measurements
AU - Zhang, Ying
AU - Zhao, Zhiqiang
AU - Feng, Zhuo
N1 - Publisher Copyright:
© 1982-2012 IEEE.
PY - 2023/4/1
Y1 - 2023/4/1
N2 - This work introduces a highly scalable spectral graph densification (SGL) framework for learning resistor networks with linear measurements, such as node voltages and currents. We show that the proposed graph learning approach is equivalent to solving the classical graphical Lasso problems with Laplacian-like precision matrices. We prove that given O(N) pairs of voltage and current measurements, it is possible to recover sparse N -node resistor networks that can well preserve the effective resistance distances on the original graph. In addition, the learned graphs also preserve the structural (spectral) properties of the original graph, which can potentially be leveraged in many circuit design and optimization tasks. To achieve more scalable performance, we also introduce a solver-free method (SF-SGL) that exploits multilevel spectral approximation of the graphs and allows for a scalable and flexible decomposition of the entire graph spectrum (to be learned) into multiple different eigenvalue clusters (frequency bands). Such a solver-free approach allows us to more efficiently identify the most spectrally critical edges for reducing various ranges of spectral embedding distortions. A unique property of the learned graphs is that the spectral embedding or effective-resistance distances on the constructed graph will encode the similarities between the original input data points (node voltage measurements). Through extensive experiments for a variety of real-world test cases, we show that the proposed approach is highly scalable for learning sparse resistor networks without sacrificing the solution quality. We also introduce a data-driven EDA algorithm for vectorless power/thermal integrity verifications to allow estimating worst case voltage/temperature (gradient) distributions across the entire chip by leveraging a few voltage/temperature measurements.
AB - This work introduces a highly scalable spectral graph densification (SGL) framework for learning resistor networks with linear measurements, such as node voltages and currents. We show that the proposed graph learning approach is equivalent to solving the classical graphical Lasso problems with Laplacian-like precision matrices. We prove that given O(N) pairs of voltage and current measurements, it is possible to recover sparse N -node resistor networks that can well preserve the effective resistance distances on the original graph. In addition, the learned graphs also preserve the structural (spectral) properties of the original graph, which can potentially be leveraged in many circuit design and optimization tasks. To achieve more scalable performance, we also introduce a solver-free method (SF-SGL) that exploits multilevel spectral approximation of the graphs and allows for a scalable and flexible decomposition of the entire graph spectrum (to be learned) into multiple different eigenvalue clusters (frequency bands). Such a solver-free approach allows us to more efficiently identify the most spectrally critical edges for reducing various ranges of spectral embedding distortions. A unique property of the learned graphs is that the spectral embedding or effective-resistance distances on the constructed graph will encode the similarities between the original input data points (node voltage measurements). Through extensive experiments for a variety of real-world test cases, we show that the proposed approach is highly scalable for learning sparse resistor networks without sacrificing the solution quality. We also introduce a data-driven EDA algorithm for vectorless power/thermal integrity verifications to allow estimating worst case voltage/temperature (gradient) distributions across the entire chip by leveraging a few voltage/temperature measurements.
KW - Data-driven EDA
KW - graph Laplacian estimation
KW - graphical Lasso
KW - spectral graph theory
KW - vectorless verification
UR - http://www.scopus.com/inward/record.url?scp=85136855044&partnerID=8YFLogxK
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U2 - 10.1109/TCAD.2022.3198513
DO - 10.1109/TCAD.2022.3198513
M3 - Article
AN - SCOPUS:85136855044
SN - 0278-0070
VL - 42
SP - 1235
EP - 1249
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 4
ER -