TY - JOUR
T1 - SICE
T2 - Design-dependent statistical interconnect corner extraction under inter/intra-die variations
AU - Feng, Z.
AU - Li, P.
AU - Ren, Z.
PY - 2009
Y1 - 2009
N2 - While traditional worst-case corner analysis is often too pessimistic for nanometer designs, full-blown statistical circuit analysis requires significant modelling infrastructures. In this study, a design-dependent statistical interconnect corner extraction (SICE) methodology is proposed. SICE achieves a good trade-off between complexity and pessimism by extracting more than one process corners in a statistical sense, which are also design dependent. Our new approach removes the pessimism incurred in prior work while being computationally efficient. The efficiency of SICE comes from the use of parameter dimension reduction techniques. The statistical corners are further compacted by an iterative output clustering method. Numerical results show that SICE achieves up to 260X speedups over the Monte Carlo method.
AB - While traditional worst-case corner analysis is often too pessimistic for nanometer designs, full-blown statistical circuit analysis requires significant modelling infrastructures. In this study, a design-dependent statistical interconnect corner extraction (SICE) methodology is proposed. SICE achieves a good trade-off between complexity and pessimism by extracting more than one process corners in a statistical sense, which are also design dependent. Our new approach removes the pessimism incurred in prior work while being computationally efficient. The efficiency of SICE comes from the use of parameter dimension reduction techniques. The statistical corners are further compacted by an iterative output clustering method. Numerical results show that SICE achieves up to 260X speedups over the Monte Carlo method.
UR - http://www.scopus.com/inward/record.url?scp=70350506128&partnerID=8YFLogxK
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U2 - 10.1049/iet-cds.2009.0040
DO - 10.1049/iet-cds.2009.0040
M3 - Article
AN - SCOPUS:70350506128
SN - 1751-858X
VL - 3
SP - 248
EP - 258
JO - IET Circuits, Devices and Systems
JF - IET Circuits, Devices and Systems
IS - 5
ER -