Statistical static timing analysis considering process variation model uncertainty

Guo Yu, Wei Dong, Zhuo Feng, Peng Li

Research output: Contribution to journalArticlepeer-review

10 Scopus citations

Abstract

Increasing variability in modern manufacturing processes makes it important to predict the yields of chip designs at early design stage. In recent years, a number of statistical static timing analysis (SSTA) and statistical circuit optimization techniques have emerged to quickly estimate the design yield and perform robust optimization. These statistical methods often rely on the availability of statistical process variation models whose accuracy, however, is severely hampered by the limitations in test structure design, test time, and various sources of inaccuracy inevitably incurred in process characterization. To consider model characterization inaccuracy, we present an efficient importance sampling based optimization framework that can translate the uncertainty in process models to the uncertainty in circuit performance, thus offering the desired statistical best/worst case circuit analysis capability accounting for the unavoidable complexity in process characterization. Furthermore, our new technique provides valuable guidance to process characterization. Examples are included to demonstrate the application of our general analysis framework under the context of SSTA.

Original languageEnglish
Article number4627546
Pages (from-to)1880-1890
Number of pages11
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume27
Issue number10
DOIs
StatePublished - Oct 2008

Keywords

  • Modeling
  • Optimization
  • Process variation

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