THREE-DIMENSIONAL FINITE ELEMENT MODELING OF FLIP CHIP PACKAGES UNDER THERMAL LOADING

In this study, both two-dimensional and three-dimensional finite element analyses were used to study the stress distribution in and deflection of the flip chip assembly under thermal loading. It is found that the three-dimensional results compared favorably with experimental measurements, while the two-dimensional results consistently overestimate both stresses and deflection. Among the two-dimensional models, plane stress assumption seems to yield results closer to the full three-dimensional predictions. Furthermore, three-dimensional models were used to investigate the effect of printed wiring board size on the overall deflection of the flip-chip assembly. This size effect of the printed wiring board has significant implications on the design of multi-chip modules. The results indicate that a square array placement pattern is preferable to a staggered array for multiple chip modules in order to reduce mechanical interaction between chips. For square arrays, such mechanical interaction between chips can be neglected when the minimum distance between adjacent chips is more than 2 times the chip size.