TY - GEN
T1 - Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation
AU - Zeng, Zhiyu
AU - Ye, Xiaoji
AU - Feng, Zhuo
AU - Li, Peng
PY - 2010
Y1 - 2010
N2 - Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates systemlevel power management. The quantitative understanding of such complex power delivery networks (PDNs) is hampered by the large network complexity and interactions between passive on-die/package-level circuits and a multitude of nonlinear active regulators. We develop a fast combined GPU-CPU analysis engine encompassing several simulation strategies, optimized for various subcomponents of the network. Using accurate quantitative analysis, we demonstrate the significant performance improvement brought by onchip low-dropout regulators (LDOs) in terms of suppressing high-frequency local voltage droops and avoiding the mid-frequency resonance caused by off-chip inductive parasitics. We perform comprehensive analysis on the tradeoffs among overhead of on-chip LDOs, maximum voltage droop and overall power efficiency. We conduct systematic design optimization by developing a simulation-based nonlinear optimization strategy that determines the optimal number of on-chip LDOs required and on-board input voltage, and the corresponding voltage droop and power efficiency for PDNs with multiple power domains.
AB - Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates systemlevel power management. The quantitative understanding of such complex power delivery networks (PDNs) is hampered by the large network complexity and interactions between passive on-die/package-level circuits and a multitude of nonlinear active regulators. We develop a fast combined GPU-CPU analysis engine encompassing several simulation strategies, optimized for various subcomponents of the network. Using accurate quantitative analysis, we demonstrate the significant performance improvement brought by onchip low-dropout regulators (LDOs) in terms of suppressing high-frequency local voltage droops and avoiding the mid-frequency resonance caused by off-chip inductive parasitics. We perform comprehensive analysis on the tradeoffs among overhead of on-chip LDOs, maximum voltage droop and overall power efficiency. We conduct systematic design optimization by developing a simulation-based nonlinear optimization strategy that determines the optimal number of on-chip LDOs required and on-board input voltage, and the corresponding voltage droop and power efficiency for PDNs with multiple power domains.
KW - Low-dropout regulator
KW - On-chip voltage regulation
KW - Power delivery network
KW - Power efficiency
UR - http://www.scopus.com/inward/record.url?scp=77956219103&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77956219103&partnerID=8YFLogxK
U2 - 10.1145/1837274.1837483
DO - 10.1145/1837274.1837483
M3 - Conference contribution
AN - SCOPUS:77956219103
SN - 9781450300025
T3 - Proceedings - Design Automation Conference
SP - 831
EP - 836
BT - Proceedings of the 47th Design Automation Conference, DAC '10
T2 - 47th Design Automation Conference, DAC '10
Y2 - 13 June 2010 through 18 June 2010
ER -